1. Field of the Invention
This invention generally relates to analog-to-digital converters (ADCs) and, more particularly, to a multiplying digital-to-analog converter (MDAC) capable of minimizing charge kickback between sampling clock cycles.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a pipelined analog-to-digital converter (ADC) (prior art). The pipelined ADC uses analog preprocessing to divide the input range into subintervals and to amplify the signal inside them. The architecture has evolved by making use of the strengths of the switched capacitor technique, which provides very accurate and linear analog amplification and summation operations in the discrete time domain. As a result, a sawtooth-shaped transfer function can readily be realized. In a pipelined ADC, m units (pipeline stages) are cascaded. Each stage processes the same sample only for one clock cycle, after which it passes it to the next stage for further processing.
The principle in pipelined analog-to-digital (A/D) conversion is to find a set of reference voltages whose sum equals the signal sample being converted. This is realized by sequentially subtracting different reference voltages from the sample until the residue becomes zero, indicating that the sum of the subtracted references equals the original sample value. An analogy can be found in weighing flour on a pair of scales using a set of weights. The residue is amplified between the subtraction steps in order to increase accuracy. The final conversion result is the sum of the subtracted reference voltages.
A functional block diagram of one stage is shown in the inset 100. The incoming voltage is sampled by the sample-and-hold (S/H) circuit 102 and simultaneously digitized by the sub-ADC 104. The result of the A/D conversion is immediately converted back to analog form and subtracted from the sampled-and-held signal. The resulting residue voltage is amplified by Gi, which is nominally equal to 2 k. In a switched capacitor realization the S/H operation, the D/A conversion, the subtraction, and the amplification are all performed by a single circuit block called a multiplying digital-to-analog converter (MDAC), which consists of an opamp and a set of switched capacitors. The low resolution sub-ADC is usually a flash, consisting of a few comparators and logic gates.
A 9-bit ADC can be realized with the standard 1.5 bits-per-stage pipeline architecture, where the 0.5 bit redundancy in each stage is used for digital correction. Each pipeline stage performs a coarse (in this case three-level) A/D conversion for its input signal and passes the amplified quantization error to the next stage. The quantization error (or residue) is formed by converting the quantization result back to analog form and subtracting it from the input signal. The residue formation and its precise amplification are performed by the MDAC.
FIG. 2 is a schematic diagram of a conventional multiplying digital-to-analog converter (prior art). The operation of the pipeline stage consists of two phases each lasting half a clock cycle. As demonstrated using the two effective bit single-ended design, in the first (sample) clock phase the MDAC samples the input signal using capacitors 200 and 202, where reference designator 200 represents three equal-valued units 200 in parallel, while 202 is only one unit. The sub-ADC (not shown) does the A/D conversion and supplies a code signal. During the second (amplify) clock phase the MDAC generates and amplifies the residue, yielding the input signal for the next stage. The charge in the input capacitors 200 is transferred to the feedback capacitor 202. The D/A operation is realized by connecting capacitors 200 to the reference voltages according to the bit code produced by the sub A/D converter.
Returning to FIG. 1, a S/H circuit is often used in front of a pipelined ADC. A front-end S/H separates the sampling from the digitization allowing the designer better optimize it for the task. However, an additional circuit block without any gain in front of the ADC means that to achieve the same noise level than without it, the capacitor sizes in the ADC front-end must be increased. This, together with the additional S/H circuit power, leads to a significant power penalty.
In contrast, when the S/H circuit is omitted, the signal is sampled directly by the first ADC stage, which now is responsible for directly sampling the input signal and determining the load for the circuit driving the ADC. The task of the driver becomes especially hard if the current drawn by the ADC input has a nonlinear dependency on the input voltage. A dominant source of nonlinear input current is a charge kickback from the sampling capacitors when they are connected to the input to take a new sample.
Another related issue with the ADC has to do with reference voltages, which are used in the analog-to-digital conversion process. The accuracy of the reference voltage has a direct effect on the accuracy of the conversion. For this reason a significant amount of power is often used in the reference voltage drivers to provide references with low noise and low signal dependent ripple. The ADC is often driven by a circuit that uses a higher operating voltage than the ADC. For this reason the driver is capable of providing a higher signal swing than the ADC can support internally. While the internal analog signal swing in the ADC is limited by the supply voltage and the voltage headroom required by the active circuit elements such as the operational amplifiers, the ADC input signal has much smaller headroom requirements and could be higher. A higher input signal swing directly translates to a higher signal-to-noise ratio (SNR). The prior art MDAC structure fixes the ADC reference voltage, internal signal swing, and input signal swing all to same value.
It would be advantageous if the MDAC input current could be made more linear during the sample clock cycle by eliminating the charge kickback associated with the sampling capacitors.
It would be advantageous if the reference voltages could be made more stable by making the loading of the current drawn by the MDAC independent of the analog input signal. Further, it would be advantageous if the range of the reference voltages could be increased with respect to the MDAC analog output signal, while decreasing the reference capacitor sizes.
It would be advantageous if the MDAC reference voltages, internal signal swing, and analog output signal swing could be decoupled from each other and set independently.